Author : AHMED SAEED ABDELSAMEA SAYED
CoAuthors : Mohamed E. Elbably, Gamal Abd-Elfadeel, Mohamed I. Eladawy
Source : WAV'09 Proceedings of the 3rd WSEAS international symposium on Wavelets theory and applications in applied mathematics, signal processing & modern science
Date of Publication : 01/2009
Abstract :
The Fast Fourier Transform (FFT) is very important algorithm in signal processing, softwaredefined radio, and wireless communication. This paper explains the realization of radix-2
2
single-path delay
feedback pipelined FFT processor. This architecture has the same multiplicative complexity as radix-4
algorithm, but retains the simple butterfly structure of radix-2 algorithm. The implementation was made on a
Field Programmable Gate Array (FPGA) because it can achieve higher computing speed than digital signal
processors (DSPs), and also can achieve cost effectively ASIC-like performance with lower development time,
and risks. The processor has been developed using hardware description language VHDL and simulated up to
465 MHz on an Xilinx xc5vsx35t for transformation length 256-point.
Download PDF